Commit 64c2a179 authored by Mike Dyer's avatar Mike Dyer Committed by Greg Kroah-Hartman

ASoC: wm8960: Fix PLL register writes

commit 85fa532b6ef920b32598df86b194571a7059a77c upstream.

Bit 9 of PLL2,3 and 4 is reserved as '0'. The 24bit fractional part
should be split across each register in 8bit chunks.
Signed-off-by: default avatarMike Dyer <mike.dyer@md-soft.co.uk>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent a7179b89
...@@ -790,9 +790,9 @@ static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, ...@@ -790,9 +790,9 @@ static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
if (pll_div.k) { if (pll_div.k) {
reg |= 0x20; reg |= 0x20;
snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 18) & 0x3f); snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff);
snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 9) & 0x1ff); snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff);
snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0x1ff); snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff);
} }
snd_soc_write(codec, WM8960_PLL1, reg); snd_soc_write(codec, WM8960_PLL1, reg);
......
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