Commit 64c2a179 authored by Mike Dyer's avatar Mike Dyer Committed by Greg Kroah-Hartman

ASoC: wm8960: Fix PLL register writes

commit 85fa532b6ef920b32598df86b194571a7059a77c upstream.

Bit 9 of PLL2,3 and 4 is reserved as '0'. The 24bit fractional part
should be split across each register in 8bit chunks.
Signed-off-by: default avatarMike Dyer <>
Signed-off-by: default avatarMark Brown <>
Signed-off-by: default avatarGreg Kroah-Hartman <>
parent a7179b89
......@@ -790,9 +790,9 @@ static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
if (pll_div.k) {
reg |= 0x20;
snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 18) & 0x3f);
snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 9) & 0x1ff);
snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0x1ff);
snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff);
snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff);
snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff);
snd_soc_write(codec, WM8960_PLL1, reg);
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment